1. Field of the Invention
This invention relates to computer systems and more particularly to interrupt controllers and power management within computer systems.
2. Background of the Relevant Art
An on-going developmental goal of manufacturers has been to reduce the power consumption of computer systems. Reducing power consumption typically reduces heat generation of the system, thereby increasing reliability and decreasing cost. In addition, power reduction has been particularly important in maximizing the operating life of battery-powered portable computer systems.
Various techniques have been devised for reducing the power consumption of computer systems. These techniques include increasing the integration of circuitry and incorporation of improved circuitry and power management units (PMU's). One specific power reduction technique involves the capability of stopping (or reducing the frequency of) clock signals that drive inactive circuit portions. A system employing such a technique typically includes a power management unit that detects or predicts inactive circuit portions and accordingly stops the clock signals associated with the inactive circuit portions. By turning off "unused" clock signals that drive inactive circuit portions, overall power consumption of the system is decreased. A similar technique involves removing the power supplied to inactive circuit portions.
The power management techniques of stopping unused clock signals and/or removing power from inactive circuit portions as described above are frequently employed within interrupt driven systems. In an interrupt driven system, peripheral and I/O devices such as keyboards, displays, timers, sensors and other components execute certain tasks independently of the central source or microprocessor, but require communication with the microprocessor at irregular, random and therefore asynchronous intervals. In such systems, a particular peripheral or I/O device generates an interrupt signal which is passed on to the microprocessor via a dedicated interrupt line or channel to request that the microprocessor interrupt its processing and communicate with the particular peripheral or I/O device. Upon detecting an active interrupt request, the microprocessor transfers control to service the particular request.
A microprocessor typically services many peripheral devices over a single input-output channel which can only be utilized by one peripheral at a time. Consequently, a priority is assigned to the various peripheral devices to discriminate between concurrent interrupt requests to service the most urgent before the others. Conventional systems have dealt with the problem of multiple interrupt sources by providing an interface circuit between the microprocessor and the peripherals to centrally sort, prioritize and control the interrupt sequencing. One such circuit is the 8259A series programmable interrupt controller manufactured by Advanced Micro Devices, Inc. and described in the publication "MOS Microprocessors and Peripherals"; pp. 3-371 through 3-388 (Advanced Micro Devices, Inc. 1987). This publication is incorporated herein by reference in its entirety.
Most interrupt controllers handle interrupt requests from eight or more peripherals or I/O devices. Each interrupt source is provided an interrupt service routine at a specified vectoral address for servicing the interrupt request. Each interrupt source has its own interrupt request line, and programmable controllers such as the 8259A allow for identification and prioritization of the various sources upon system initialization. In typical operation, the interrupt controller recognizes interrupt requests and passes the highest priority request to the microprocessor, while holding lower priority requests until the processor has completed servicing the interrupt in progress.
When a power management unit within an interrupt driven system including an interrupt controller has stopped the clock signals associated with, for example, the microprocessor, the memory subsystems, and/or other inactive peripherals, the power management unit typically monitors the interrupt request lines. If an interrupt request signal is detected, the power management unit re-starts the clock signals of the microprocessor and other peripheral components to thereby allow execution of the interrupt service routine. Since the power management unit is typically unaware of when a particular interrupt service routine has completed in such systems, the power management unit is programmed to re-stop the clock signals after an estimated period of time has elapsed. To ensure that the interrupt service routine has ample time to complete before the clock is re-stopped, the power management unit usually keeps the associated clock signals on substantially beyond the time at which the interrupt routine actually completes. In such a system, however, power is wasted when the clock signal is driven beyond the actual time of servicing the interrupt. A similar consideration applies to a situation in which the power management unit has removed power from a particular circuit portion.